SOC-PLL design requires trade-offs
نویسنده
چکیده
PLLs (phase-locked loops) are common analog circuits in SOCs (systems on chips). Almost all SOCs with a clock rate greater than 30 MHz use a PLL for frequency synthesis. However, a “one-size-fis-all” PLL does not exist. The devices have a range of frequency, power, area, performance, and functions. PLLs implemented in 100 nm or smaller processes typically range in frequency from 10 MHz to 10 GHz. Their power spans from less than 1 mW to more than 100 mW. Their size can vary from 0.04 to 2 mm2, and their performance, which you typically measure as output jitter, ranges from more than 100 fsec to more than 10 psec.
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